Digital display units required to be compatible to analog displays need to convert the received analog data into a sequence of pixel data. In general, a pixel clock is not provided together with the analog data by the video interface, but such pixel clock needs to be recovered from other clock signals, such as the horizontal sync clock, which has much lower frequency.
A typical digital display interface configured to receive analog display data is shown in FIG. 1. The video interface 101 sends analog data signals 112 synchronized with a sync clock 110 with a frequency in general much lower than the pixel rate. The analog data 112 is digitized by an analog-to-digital converter (ADC) module 140 comprising one or more analog-to-digital converters (ADC). The ADC module has only a certain window during each pixel clock period in which to sample the correct analog data. Therefore, a phase-locked loop (PLL) device 130 is required to regenerate a pixel clock 120 for the digital display unit and synchronize this pixel clock to the input sync signal. In most applications, the phase of the ADC sample clock 111 also needs to be adjusted with a resolution much finer than one pixel clock to provide the best timing window for the sampling of the incoming analog signals.
In principle, a phase-locked loop (PLL) can be used to generate a pixel clock synchronized to the input sync clock. However, the multiplication factor is larger than the number of pixels per line, which can easily be larger than 1,000, for example, and such a large multiplication number determines a large long term jitter in an analog PLL approach.
A solution for the pixel clock regeneration, proposed in U.S. Pat. No. 6,320,574, uses a digital PLL driven by an external stable clock, such as a crystal oscillator, together with an analog filter to reduce the phase jumps out of the pure digital PLL. While this solution achieves good long term stability of the recovered pixel clock, the implementation appears to require a somewhat complicated digital synthesizer and several analog components, such as a digital-to-analog converter (DAC), a reconstruction filter, and an analog PLL as a clock output filter and frequency multiplier. The described early/late phase detector does not have the capability of resolving phase difference smaller than one reference clock cycle, which is fairly coarse, and will determine large jitter in the output clock, therefore requiring an analog output filter. Another limitation is the maximum rate if the synthesized clock is only a fraction of the reference clock. Therefore, for most common applications, this solution requires a frequency multiplication in the analog output filter.
An all digital PLL, previously proposed in U.S. Pat. No. 6,628,276, avoids the use of any analog components, therefore being more robust to various process technology changes. This implementation, however, appears to require a relatively high frequency input reference clock, with at least twice the frequency of the output pixel rate, and complicated digital subsystems such as a high precision digital phase comparator and a delay lock loop (DLL). The described high precision digital phase comparator has very good resolution, but has only a finite phase detection range, and, therefore, other state machines have to detect when the phase error is small enough for the output of the high precision phase detector is valid. Also, the actual delay elements in the high precision phase comparator have to match the delay in the pixel clock synthesizer, so the phase error tracks the pixel clock rate. The described implementation is rather complex, requiring several delay lines and a fast reference clock, which would be in fact generated by an analog clock multiplier or PLL.
Thus, in a real application, it would be advantageous to provide an implementation that can handle large possible phase errors, even after lock capturing, especially in a noisy environment, where the jitter in the input sync clock can be actually larger than a pixel clock period.